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publications
HAPM - Hardware Aware Pruning Method for CNN hardware accelerators in resource constrained devices
Published in arXiv, 2021
Paper result from the thesis for the title of Electronic Engineer attained in 2021 at the Universidad Tecnologica Nacional (UTN), Argentina.
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Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework
Published in ESWEEK Workshop: CODAI 2023, 2022
This paper explains the integration added to the TVM framework to generate C code to accelerate neural networks on the Gemmini accelerator
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Low-Power Traffic Surveillance using Multiple RGB and Event Cameras: A Survey
Published in IEEE International Smart Cities Conference (ISC2) 2023, 2023
This paper presents a survey on methods and techniques for traffic surveillance using multiple POV cameras.
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Characterization of Execution Time Variability in FPGA-Based AI-Accelerators
Published in 2023 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf on Cloud and Big Data Computing, Intl Conf on Cyber Science and Technology Congress (DASC/PiCom/CBDCom/CyberSciTech), 2023
This paper presents a comparison of execution time of different Neural Networks on different FPGA-based open source AI Accelerators.
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DIAPASON: Differentiable Allocation, Partitioning and Fusion of Neural Networks for Distributed Inference
Published in Design, Automation and Test in Europe Conference, 2024
This paper presents a new method to model the problem of distributing the inference of a NN across multiple devices.
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Iterative Filter Pruning for Concatenation-based CNN Architectures
Published in , 2024
A method to prune in an iterative manner CNNs, taking into account the connectivity graph of layers.
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Embedded Distributed Inference of Deep Neural Networks: A Systematic Review
Published in arXiv, 2024
This paper presents a systematic review of papers distributing the execution of CNNs across multiple devices.
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Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Accelerator
Published in 27th Euromicro Conference Series on Digital System Design (DSD) 2024, 2024
This paper presents a workflow for deployment of CNNs on custom hardware accelerators, taken into account pruning, quantization, and tuning. The workflow was realized using TVM.
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talks
teaching
Teaching assistant at UTN, course “Digital Techniques 3”
Graduate course, National Technological University (UTN), Department of Electronics, 2021
I was a teaching assistant on course “Digital Techniques 3”, working for Prof. Ing. Alejandro Furfaro. I was in charge of the applied side of the course, where we worked on baremetal programming and embedded Linux for ARM.